About Me:

Hello, welcome to my home page. I am an Assistant Professor at the Department of CSE, Indian Institute of Technology Ropar, Punjab. My academic details and experiences are as follows:

  1. Assistant Professor: Department of CSE, Indian Institute of Technology Ropar, Punjab (June 2018 - till date).
  2. Assistant Professor: Department of CSE, Indian Institute of Information Technology Guwahati, Assam (August 2015 - June 2018).
  3. PhD from Indian Institute of Technology Guwahati in January 2016.
    Thesis Title: "Effective Utilization of LLCs by Managing Associativity, Placement and Mapping" (LLC means Last Level Cache).
    PhD Supervisor: Prof. Hemangee K. Kapoor.
  4. M.Tech (in CSE) from Indian Institute of Technology Guwahati in July 2010.
  5. MSc in Computer Science from Assam University Silchar, Assam in June 2007.


Research Interests:

My current research focus is on Chip-multiprocessors (CMP) specifically the issues of Last Level Cache (LLC), Network on Chip (NoC) and DRAM Caches. Some of the issues are mentioned bellow:

  1. Performance enhancement of LLCs in Tiled Based CMPs (TCMP).
  2. Minimising the on-chip communication latency in TCMP.
  3. Energy consumption and temperature optimisation of LLC, NoC and DRAM cache memories.
  4. Smart replacement policies for different NUCA (Non Uniform Cache Access) based cache memory architectures.
The simulation tools require for my research include: GEMS, SIMICS, Gem5, Booksim, McPAT, CACTI, HotSpot, Garnet and Orion etc.

I did my MTech in Formal Verification. During my MTech, I have designed a mathematical model for the multi-clock latency insensitive systems. I have plan to work on formal verification for cache coherence protocols used in TCMP.

Research Project: One of my project entitled, "Reducing Energy Consumption and Operating Temperature of Last Level DRAM Cache in Multicore Systems" has been approved by the Govt. of India, Science and Engineering Research Board (SERB), under the Early Career Research Award scheme. It is a three years project (July 2017 - June 2020).

Teaching:

Teaching at IIT Ropar:

  1. [Aug'18 - Nov'18]: Tinkering Lab and Introduction to Engineering Product Lab.
  2. [Aug'18 - Nov'18]: Data structure for non-CSE students.
I have experience (before joining IIT Ropar) of teaching courses like Compilers, DBMS, Theory of Computation, Advance Architecture etc.

Professional Activities:

  1. Reviewer: MICPRO, TPDS and IET Computers & Digital Techniques.

Publications:

Journals
  1. Dipika Deb, John Jose , Shirshendu Das and H. K. Kapoor, “Cost Effective Routing Techniques in 2D Mesh NoC using On-Chip Transmission Lines,” Elsevier Journal of Parallel and Distributed Computing (JPDC), Accepted in September, 2018. Journal ranking: A* (ERA), Q1 (scimagojr).
  2. Shirshendu Das and H. K. Kapoor, “Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets,” IEEE Transactions on Parallel and Distributed Systems (TPDS), 28(8), 2017, 2229-2243. Journal ranking: A* (ERA), Q1 (scimagojr).
  3. Shirshendu Das and H. K. Kapoor, “A Framework for Block Placement, Migration and Fast Searching in Tiled-DNUCA Architecture,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 22(1), 2016. Journal ranking: A (ERA), Q2 (scimagojr).
  4. Shirshendu Das and H. K. Kapoor, “Victim Retention for Reducing Cache Misses in Tiled Chip Multiprocessors,” Journal of Microprocessors and Microsystems (Elsevier), 38 (4), (2014), 263–275. Journal ranking: Q3 (scimagojr).
  5. Shirshendu Das, P. S. Duggirala, and H. K. Kapoor, “A formal framework for interfacing mixed-timing systems,” Integration, the VLSI Journal (Elsevier), 46 (3), (2013). 255-264. Journal ranking: Q3 (scimagojr).
  6. H. K. Kapoor, P. Kanakala, M. Verma, and S. Das, “Design and formal verification of a hierarchical cache coherence protocol for noc based multiprocessors,” The Journal of Supercomputing (Springer), 65 (2), 2013, 771-796. Journal ranking: B (ERA), Q2 (scimagojr).
Conferences
  1. Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor, "Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors," VLSI Design 2018, 31-36.
  2. Shirshendu Das and Hemangee K. Kapoor, "Latency Aware Block Replacement for L1 Caches in Chip MultiProcessors," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Bochum, Germany.
  3. Shirshendu Das and Hemangee K. Kapoor, "Dynamic Associativity Enabled DNUCA to Improve Block Localisation in Tiled CMPs," 31st ACM/SIGAPP Symposium On Applied Computing (ACM-SAC), 2016, Pisa, Italy.  
  4. Shounak Chakraborty, Shirshendu Das and Hemangee Kapoor, "Static Energy Efficient Cache Reconfiguration for Dynamic NUCA in Tiled CMPs," 31st ACM/SIGAPP Symposium on Applied Computing (ACM-SAC), 2016, Pisa, Italy.
  5. Shirshendu Das and Hemangee K. Kapoor, "Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches," 29th International Conference on VLSI Design-2016 (VLSID), 2016, Kolkata, India.
  6. Shounak Chakraborty, Shirshendu Das and Hemangee K. Kapoor, "Performance constrained static energy reduction using way-sharing target-banks," 17th Workshop on Advances on Parallel and Distributed Processing Symposium (APDCM), in conjunction with IPDPS, 2015, Hydrabad, India.
  7. Shirshendu Das and Hemangee K. Kapoor, "Dynamic Associativity Management Using Utility Based Way-Sharing," 30th ACM/SIGAPP Symposium On Applied Computing (ACM-SAC), 2015, Salamanca, Spain.
  8. Hemangee Kapoor, Shirshendu Das and Shounak Chakraborty, "Static energy reduction by performance linked cache capacity management in Tiled CMPs," 30th ACM/SIGAPP Symposium on Applied Computing (ACM-SAC), 2015, Salamanca, Spain.
  9. Shirshendu Das and Hemangee K. Kapoor, "Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs," 28th International Conference on VLSI Design (VLSID), 2015, Bangalore, India.
  10. Mojjada Lakshmi Prasad, Shirshendu Das and Hemangee K. Kapoor, "An Approach for Multicast Routing in Networks-on-Chip," 13th International Conference on Information Technology (ICIT), 2014, Bhubaneswar, India.
  11. Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor, "Towards a Better Cache Utilization Using Controlled Cache Partitioning," 11th IEEE International Conference on Embedded Computing (EmbeddedCom), 2013, Chengdu, China. 
  12. S. Das and H. K. Kapoor, "Dynamic associativity management using fellow sets," 4th International Symposium on Electronic System Design (ISED), 2013, NTU Singapore.

Other Activities:

I am an adventure loving person. I like cycling, trekking, road trip etc. It is my dream to travel all over India with my cycle and motorcycle :) . I also love to play badminton, football, and cricket.

Mountain View

Dr. Shirshendu Das

Assistant Professor

Department of CSE

IIT Ropar, Punjab, India.

shirshendu[at]iitrpr.ac.in

+919435277250